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[DAG] visitINSERT_VECTOR_ELT - create BUILD_VECTOR from insert(insert(freeze(undef),s0,0),s1,1) style chain #146644

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[DAG] visitINSERT_VECTOR_ELT - create BUILD_VECTOR from insert(insert(freeze(undef),s0,0),s1,1) style chain #146644

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@RKSimon RKSimon commented Jul 2, 2025

We already create BUILD_VECTOR nodes from INSERT_VECTOR_ELT chains that begin with an undef vector base - this patch adds support for a freeze(undef) variant as well.

Pulled out of #145939 which encourages their generation by pushing freezes up through the chain

@RKSimon
[DAG] visitINSERT_VECTOR_ELT - create BUILD_VECTOR from insert(insert…
0db145b 
…(freeze(undef),s0,0),s1,1) style chain

We already create BUILD_VECTOR nodes from INSERT_VECTOR_ELT chains that begin with an undef vector base - this patch adds support for a freeze(undef) variant as well.

Pulled out of llvm#145939 which encourages their generation by pushing freezes up through the chain
@RKSimon RKSimon requested review from arsenm, nikic and bjope July 2, 2025 07:38
@llvmbot llvmbot added backend:SystemZ llvm:SelectionDAG SelectionDAGISel as well labels Jul 2, 2025
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llvmbot commented Jul 2, 2025

@llvm/pr-subscribers-llvm-selectiondag

Author: Simon Pilgrim (RKSimon)

Changes

We already create BUILD_VECTOR nodes from INSERT_VECTOR_ELT chains that begin with an undef vector base - this patch adds support for a freeze(undef) variant as well.

Pulled out of #145939 which encourages their generation by pushing freezes up through the chain

Full diff: https://github.com/llvm/llvm-project/pull/146644.diff

2 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+8-1)
  • (modified) llvm/test/CodeGen/SystemZ/pr60413.ll (+47-53)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index bfc061b404560..92d1098f43856 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -23184,11 +23184,14 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
 
     // Ensure all the operands are the same value type, fill any missing
     // operands with UNDEF and create the BUILD_VECTOR.
-    auto CanonicalizeBuildVector = [&](SmallVectorImpl<SDValue> &Ops) {
+    auto CanonicalizeBuildVector = [&](SmallVectorImpl<SDValue> &Ops,
+                                       bool FreezeUndef = false) {
       assert(Ops.size() == NumElts && "Unexpected vector size");
       for (SDValue &Op : Ops) {
         if (Op)
           Op = VT.isInteger() ? DAG.getAnyExtOrTrunc(Op, DL, MaxEltVT) : Op;
+        else if (FreezeUndef)
+          Op = DAG.getFreeze(DAG.getUNDEF(MaxEltVT));
         else
           Op = DAG.getUNDEF(MaxEltVT);
       }
@@ -23204,6 +23207,10 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
       if (CurVec.isUndef())
         return CanonicalizeBuildVector(Ops);
 
+      // FREEZE(UNDEF) - build new BUILD_VECTOR from already inserted operands.
+      if (ISD::isFreezeUndef(CurVec.getNode()))
+        return CanonicalizeBuildVector(Ops, /*FreezeUndef=*/true);
+
       // BUILD_VECTOR - insert unused operands and build new BUILD_VECTOR.
       if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) {
         for (unsigned I = 0; I != NumElts; ++I)
diff --git a/llvm/test/CodeGen/SystemZ/pr60413.ll b/llvm/test/CodeGen/SystemZ/pr60413.ll
index 6dee3d303a6f2..8a6a30318ae58 100644
--- a/llvm/test/CodeGen/SystemZ/pr60413.ll
+++ b/llvm/test/CodeGen/SystemZ/pr60413.ll
@@ -13,6 +13,7 @@ declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0
 define dso_local void @m() local_unnamed_addr #1 {
 ; CHECK-LABEL: m:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stmg %r13, %r15, 104(%r15)
 ; CHECK-NEXT:    aghi %r15, -168
 ; CHECK-NEXT:    lhrl %r1, f+4
 ; CHECK-NEXT:    sll %r1, 8
@@ -20,66 +21,59 @@ define dso_local void @m() local_unnamed_addr #1 {
 ; CHECK-NEXT:    ic %r1, 6(%r2)
 ; CHECK-NEXT:    larl %r2, e
 ; CHECK-NEXT:    lb %r0, 3(%r2)
+; CHECK-NEXT:    vlvgp %v0, %r0, %r1
+; CHECK-NEXT:    vlvgp %v1, %r1, %r0
 ; CHECK-NEXT:    vlvgf %v1, %r1, 0
-; CHECK-NEXT:    vlvgf %v1, %r1, 1
-; CHECK-NEXT:    larl %r2, .LCPI0_0
-; CHECK-NEXT:    vl %v2, 0(%r2), 3
-; CHECK-NEXT:    vlvgf %v1, %r1, 3
-; CHECK-NEXT:    vlvgf %v3, %r1, 3
-; CHECK-NEXT:    vlvgf %v0, %r1, 1
-; CHECK-NEXT:    vperm %v4, %v1, %v0, %v2
-; CHECK-NEXT:    vlvgf %v0, %r1, 3
+; CHECK-NEXT:    vlvgf %v1, %r1, 2
+; CHECK-NEXT:    vlvgp %v2, %r1, %r1
+; CHECK-NEXT:    # kill: def $r1l killed $r1l killed $r1d
 ; CHECK-NEXT:    nilh %r1, 255
 ; CHECK-NEXT:    chi %r1, 128
 ; CHECK-NEXT:    ipm %r1
 ; CHECK-NEXT:    risbg %r1, %r1, 63, 191, 36
-; CHECK-NEXT:    vperm %v0, %v3, %v0, %v2
-; CHECK-NEXT:    larl %r2, .LCPI0_1
-; CHECK-NEXT:    vl %v5, 0(%r2), 3
-; CHECK-NEXT:    vgbm %v6, 30583
-; CHECK-NEXT:    vn %v0, %v0, %v6
-; CHECK-NEXT:    vn %v4, %v4, %v6
-; CHECK-NEXT:    vperm %v1, %v1, %v1, %v5
-; CHECK-NEXT:    vn %v1, %v1, %v6
-; CHECK-NEXT:    vperm %v2, %v0, %v3, %v2
-; CHECK-NEXT:    vn %v2, %v2, %v6
+; CHECK-NEXT:    vlvgf %v0, %r0, 0
+; CHECK-NEXT:    vlvgf %v0, %r0, 2
+; CHECK-NEXT:    vgbm %v3, 30583
+; CHECK-NEXT:    vn %v0, %v0, %v3
+; CHECK-NEXT:    vn %v1, %v1, %v3
+; CHECK-NEXT:    vrepf %v2, %v2, 1
+; CHECK-NEXT:    vn %v2, %v2, %v3
 ; CHECK-NEXT:    vrepif %v3, 127
 ; CHECK-NEXT:    vchlf %v1, %v1, %v3
-; CHECK-NEXT:    vlgvf %r3, %v1, 1
-; CHECK-NEXT:    vlgvf %r2, %v1, 0
-; CHECK-NEXT:    risbg %r2, %r2, 48, 176, 15
-; CHECK-NEXT:    rosbg %r2, %r3, 49, 49, 14
-; CHECK-NEXT:    vlgvf %r3, %v1, 2
-; CHECK-NEXT:    rosbg %r2, %r3, 50, 50, 13
-; CHECK-NEXT:    vlgvf %r3, %v1, 3
-; CHECK-NEXT:    rosbg %r2, %r3, 51, 51, 12
-; CHECK-NEXT:    vchlf %v1, %v4, %v3
-; CHECK-NEXT:    vlgvf %r3, %v1, 0
-; CHECK-NEXT:    rosbg %r2, %r3, 52, 52, 11
-; CHECK-NEXT:    vlgvf %r3, %v1, 1
-; CHECK-NEXT:    rosbg %r2, %r3, 53, 53, 10
-; CHECK-NEXT:    vlgvf %r3, %v1, 2
-; CHECK-NEXT:    rosbg %r2, %r3, 54, 54, 9
-; CHECK-NEXT:    vlgvf %r3, %v1, 3
-; CHECK-NEXT:    rosbg %r2, %r3, 55, 55, 8
-; CHECK-NEXT:    vchlf %v1, %v2, %v3
-; CHECK-NEXT:    vlgvf %r3, %v1, 0
-; CHECK-NEXT:    rosbg %r2, %r3, 56, 56, 7
-; CHECK-NEXT:    vlgvf %r3, %v1, 1
-; CHECK-NEXT:    rosbg %r2, %r3, 57, 57, 6
-; CHECK-NEXT:    vlgvf %r3, %v1, 2
-; CHECK-NEXT:    rosbg %r2, %r3, 58, 58, 5
-; CHECK-NEXT:    vlgvf %r3, %v1, 3
-; CHECK-NEXT:    rosbg %r2, %r3, 59, 59, 4
+; CHECK-NEXT:    vlgvf %r13, %v1, 0
+; CHECK-NEXT:    vchlf %v2, %v2, %v3
+; CHECK-NEXT:    vlgvf %r3, %v2, 1
+; CHECK-NEXT:    nilf %r3, 1
+; CHECK-NEXT:    vlgvf %r4, %v2, 0
+; CHECK-NEXT:    risbg %r2, %r4, 48, 176, 15
+; CHECK-NEXT:    rosbg %r2, %r3, 32, 49, 14
+; CHECK-NEXT:    vlgvf %r5, %v2, 2
+; CHECK-NEXT:    nilf %r5, 1
+; CHECK-NEXT:    rosbg %r2, %r5, 32, 50, 13
+; CHECK-NEXT:    vlgvf %r14, %v2, 3
+; CHECK-NEXT:    nilf %r14, 1
+; CHECK-NEXT:    rosbg %r2, %r14, 32, 51, 12
+; CHECK-NEXT:    rosbg %r2, %r13, 52, 52, 11
+; CHECK-NEXT:    vlgvf %r13, %v1, 1
+; CHECK-NEXT:    rosbg %r2, %r13, 53, 53, 10
+; CHECK-NEXT:    vlgvf %r13, %v1, 2
+; CHECK-NEXT:    rosbg %r2, %r13, 54, 54, 9
+; CHECK-NEXT:    vlgvf %r13, %v1, 3
+; CHECK-NEXT:    rosbg %r2, %r13, 55, 55, 8
 ; CHECK-NEXT:    vchlf %v0, %v0, %v3
-; CHECK-NEXT:    vlgvf %r3, %v0, 0
-; CHECK-NEXT:    rosbg %r2, %r3, 60, 60, 3
-; CHECK-NEXT:    vlgvf %r3, %v0, 1
-; CHECK-NEXT:    rosbg %r2, %r3, 61, 61, 2
-; CHECK-NEXT:    vlgvf %r3, %v0, 2
-; CHECK-NEXT:    rosbg %r2, %r3, 62, 62, 1
-; CHECK-NEXT:    vlgvf %r3, %v0, 3
-; CHECK-NEXT:    rosbg %r2, %r3, 63, 63, 0
+; CHECK-NEXT:    vlgvf %r13, %v0, 0
+; CHECK-NEXT:    rosbg %r2, %r13, 56, 56, 7
+; CHECK-NEXT:    vlgvf %r13, %v0, 1
+; CHECK-NEXT:    rosbg %r2, %r13, 57, 57, 6
+; CHECK-NEXT:    vlgvf %r13, %v0, 2
+; CHECK-NEXT:    rosbg %r2, %r13, 58, 58, 5
+; CHECK-NEXT:    vlgvf %r13, %v0, 3
+; CHECK-NEXT:    rosbg %r2, %r13, 59, 59, 4
+; CHECK-NEXT:    nilf %r4, 1
+; CHECK-NEXT:    rosbg %r2, %r4, 32, 60, 3
+; CHECK-NEXT:    rosbg %r2, %r3, 32, 61, 2
+; CHECK-NEXT:    rosbg %r2, %r5, 32, 62, 1
+; CHECK-NEXT:    or %r2, %r14
 ; CHECK-NEXT:    vlgvb %r4, %v0, 1
 ; CHECK-NEXT:    vlgvb %r3, %v0, 0
 ; CHECK-NEXT:    risbg %r3, %r3, 48, 176, 15
@@ -122,7 +116,7 @@ define dso_local void @m() local_unnamed_addr #1 {
 ; CHECK-NEXT:    nr %r2, %r0
 ; CHECK-NEXT:    larl %r1, g
 ; CHECK-NEXT:    stc %r2, 0(%r1)
-; CHECK-NEXT:    aghi %r15, 168
+; CHECK-NEXT:    lmg %r13, %r15, 272(%r15)
 ; CHECK-NEXT:    br %r14
 entry:
   %n = alloca i32, align 4

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llvmbot commented Jul 2, 2025

@llvm/pr-subscribers-backend-systemz

Author: Simon Pilgrim (RKSimon)

Changes

We already create BUILD_VECTOR nodes from INSERT_VECTOR_ELT chains that begin with an undef vector base - this patch adds support for a freeze(undef) variant as well.

Pulled out of #145939 which encourages their generation by pushing freezes up through the chain

Full diff: https://github.com/llvm/llvm-project/pull/146644.diff

2 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+8-1)
  • (modified) llvm/test/CodeGen/SystemZ/pr60413.ll (+47-53)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index bfc061b404560..92d1098f43856 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -23184,11 +23184,14 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
 
     // Ensure all the operands are the same value type, fill any missing
     // operands with UNDEF and create the BUILD_VECTOR.
-    auto CanonicalizeBuildVector = [&](SmallVectorImpl<SDValue> &Ops) {
+    auto CanonicalizeBuildVector = [&](SmallVectorImpl<SDValue> &Ops,
+                                       bool FreezeUndef = false) {
       assert(Ops.size() == NumElts && "Unexpected vector size");
       for (SDValue &Op : Ops) {
         if (Op)
           Op = VT.isInteger() ? DAG.getAnyExtOrTrunc(Op, DL, MaxEltVT) : Op;
+        else if (FreezeUndef)
+          Op = DAG.getFreeze(DAG.getUNDEF(MaxEltVT));
         else
           Op = DAG.getUNDEF(MaxEltVT);
       }
@@ -23204,6 +23207,10 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
       if (CurVec.isUndef())
         return CanonicalizeBuildVector(Ops);
 
+      // FREEZE(UNDEF) - build new BUILD_VECTOR from already inserted operands.
+      if (ISD::isFreezeUndef(CurVec.getNode()))
+        return CanonicalizeBuildVector(Ops, /*FreezeUndef=*/true);
+
       // BUILD_VECTOR - insert unused operands and build new BUILD_VECTOR.
       if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) {
         for (unsigned I = 0; I != NumElts; ++I)
diff --git a/llvm/test/CodeGen/SystemZ/pr60413.ll b/llvm/test/CodeGen/SystemZ/pr60413.ll
index 6dee3d303a6f2..8a6a30318ae58 100644
--- a/llvm/test/CodeGen/SystemZ/pr60413.ll
+++ b/llvm/test/CodeGen/SystemZ/pr60413.ll
@@ -13,6 +13,7 @@ declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0
 define dso_local void @m() local_unnamed_addr #1 {
 ; CHECK-LABEL: m:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stmg %r13, %r15, 104(%r15)
 ; CHECK-NEXT:    aghi %r15, -168
 ; CHECK-NEXT:    lhrl %r1, f+4
 ; CHECK-NEXT:    sll %r1, 8
@@ -20,66 +21,59 @@ define dso_local void @m() local_unnamed_addr #1 {
 ; CHECK-NEXT:    ic %r1, 6(%r2)
 ; CHECK-NEXT:    larl %r2, e
 ; CHECK-NEXT:    lb %r0, 3(%r2)
+; CHECK-NEXT:    vlvgp %v0, %r0, %r1
+; CHECK-NEXT:    vlvgp %v1, %r1, %r0
 ; CHECK-NEXT:    vlvgf %v1, %r1, 0
-; CHECK-NEXT:    vlvgf %v1, %r1, 1
-; CHECK-NEXT:    larl %r2, .LCPI0_0
-; CHECK-NEXT:    vl %v2, 0(%r2), 3
-; CHECK-NEXT:    vlvgf %v1, %r1, 3
-; CHECK-NEXT:    vlvgf %v3, %r1, 3
-; CHECK-NEXT:    vlvgf %v0, %r1, 1
-; CHECK-NEXT:    vperm %v4, %v1, %v0, %v2
-; CHECK-NEXT:    vlvgf %v0, %r1, 3
+; CHECK-NEXT:    vlvgf %v1, %r1, 2
+; CHECK-NEXT:    vlvgp %v2, %r1, %r1
+; CHECK-NEXT:    # kill: def $r1l killed $r1l killed $r1d
 ; CHECK-NEXT:    nilh %r1, 255
 ; CHECK-NEXT:    chi %r1, 128
 ; CHECK-NEXT:    ipm %r1
 ; CHECK-NEXT:    risbg %r1, %r1, 63, 191, 36
-; CHECK-NEXT:    vperm %v0, %v3, %v0, %v2
-; CHECK-NEXT:    larl %r2, .LCPI0_1
-; CHECK-NEXT:    vl %v5, 0(%r2), 3
-; CHECK-NEXT:    vgbm %v6, 30583
-; CHECK-NEXT:    vn %v0, %v0, %v6
-; CHECK-NEXT:    vn %v4, %v4, %v6
-; CHECK-NEXT:    vperm %v1, %v1, %v1, %v5
-; CHECK-NEXT:    vn %v1, %v1, %v6
-; CHECK-NEXT:    vperm %v2, %v0, %v3, %v2
-; CHECK-NEXT:    vn %v2, %v2, %v6
+; CHECK-NEXT:    vlvgf %v0, %r0, 0
+; CHECK-NEXT:    vlvgf %v0, %r0, 2
+; CHECK-NEXT:    vgbm %v3, 30583
+; CHECK-NEXT:    vn %v0, %v0, %v3
+; CHECK-NEXT:    vn %v1, %v1, %v3
+; CHECK-NEXT:    vrepf %v2, %v2, 1
+; CHECK-NEXT:    vn %v2, %v2, %v3
 ; CHECK-NEXT:    vrepif %v3, 127
 ; CHECK-NEXT:    vchlf %v1, %v1, %v3
-; CHECK-NEXT:    vlgvf %r3, %v1, 1
-; CHECK-NEXT:    vlgvf %r2, %v1, 0
-; CHECK-NEXT:    risbg %r2, %r2, 48, 176, 15
-; CHECK-NEXT:    rosbg %r2, %r3, 49, 49, 14
-; CHECK-NEXT:    vlgvf %r3, %v1, 2
-; CHECK-NEXT:    rosbg %r2, %r3, 50, 50, 13
-; CHECK-NEXT:    vlgvf %r3, %v1, 3
-; CHECK-NEXT:    rosbg %r2, %r3, 51, 51, 12
-; CHECK-NEXT:    vchlf %v1, %v4, %v3
-; CHECK-NEXT:    vlgvf %r3, %v1, 0
-; CHECK-NEXT:    rosbg %r2, %r3, 52, 52, 11
-; CHECK-NEXT:    vlgvf %r3, %v1, 1
-; CHECK-NEXT:    rosbg %r2, %r3, 53, 53, 10
-; CHECK-NEXT:    vlgvf %r3, %v1, 2
-; CHECK-NEXT:    rosbg %r2, %r3, 54, 54, 9
-; CHECK-NEXT:    vlgvf %r3, %v1, 3
-; CHECK-NEXT:    rosbg %r2, %r3, 55, 55, 8
-; CHECK-NEXT:    vchlf %v1, %v2, %v3
-; CHECK-NEXT:    vlgvf %r3, %v1, 0
-; CHECK-NEXT:    rosbg %r2, %r3, 56, 56, 7
-; CHECK-NEXT:    vlgvf %r3, %v1, 1
-; CHECK-NEXT:    rosbg %r2, %r3, 57, 57, 6
-; CHECK-NEXT:    vlgvf %r3, %v1, 2
-; CHECK-NEXT:    rosbg %r2, %r3, 58, 58, 5
-; CHECK-NEXT:    vlgvf %r3, %v1, 3
-; CHECK-NEXT:    rosbg %r2, %r3, 59, 59, 4
+; CHECK-NEXT:    vlgvf %r13, %v1, 0
+; CHECK-NEXT:    vchlf %v2, %v2, %v3
+; CHECK-NEXT:    vlgvf %r3, %v2, 1
+; CHECK-NEXT:    nilf %r3, 1
+; CHECK-NEXT:    vlgvf %r4, %v2, 0
+; CHECK-NEXT:    risbg %r2, %r4, 48, 176, 15
+; CHECK-NEXT:    rosbg %r2, %r3, 32, 49, 14
+; CHECK-NEXT:    vlgvf %r5, %v2, 2
+; CHECK-NEXT:    nilf %r5, 1
+; CHECK-NEXT:    rosbg %r2, %r5, 32, 50, 13
+; CHECK-NEXT:    vlgvf %r14, %v2, 3
+; CHECK-NEXT:    nilf %r14, 1
+; CHECK-NEXT:    rosbg %r2, %r14, 32, 51, 12
+; CHECK-NEXT:    rosbg %r2, %r13, 52, 52, 11
+; CHECK-NEXT:    vlgvf %r13, %v1, 1
+; CHECK-NEXT:    rosbg %r2, %r13, 53, 53, 10
+; CHECK-NEXT:    vlgvf %r13, %v1, 2
+; CHECK-NEXT:    rosbg %r2, %r13, 54, 54, 9
+; CHECK-NEXT:    vlgvf %r13, %v1, 3
+; CHECK-NEXT:    rosbg %r2, %r13, 55, 55, 8
 ; CHECK-NEXT:    vchlf %v0, %v0, %v3
-; CHECK-NEXT:    vlgvf %r3, %v0, 0
-; CHECK-NEXT:    rosbg %r2, %r3, 60, 60, 3
-; CHECK-NEXT:    vlgvf %r3, %v0, 1
-; CHECK-NEXT:    rosbg %r2, %r3, 61, 61, 2
-; CHECK-NEXT:    vlgvf %r3, %v0, 2
-; CHECK-NEXT:    rosbg %r2, %r3, 62, 62, 1
-; CHECK-NEXT:    vlgvf %r3, %v0, 3
-; CHECK-NEXT:    rosbg %r2, %r3, 63, 63, 0
+; CHECK-NEXT:    vlgvf %r13, %v0, 0
+; CHECK-NEXT:    rosbg %r2, %r13, 56, 56, 7
+; CHECK-NEXT:    vlgvf %r13, %v0, 1
+; CHECK-NEXT:    rosbg %r2, %r13, 57, 57, 6
+; CHECK-NEXT:    vlgvf %r13, %v0, 2
+; CHECK-NEXT:    rosbg %r2, %r13, 58, 58, 5
+; CHECK-NEXT:    vlgvf %r13, %v0, 3
+; CHECK-NEXT:    rosbg %r2, %r13, 59, 59, 4
+; CHECK-NEXT:    nilf %r4, 1
+; CHECK-NEXT:    rosbg %r2, %r4, 32, 60, 3
+; CHECK-NEXT:    rosbg %r2, %r3, 32, 61, 2
+; CHECK-NEXT:    rosbg %r2, %r5, 32, 62, 1
+; CHECK-NEXT:    or %r2, %r14
 ; CHECK-NEXT:    vlgvb %r4, %v0, 1
 ; CHECK-NEXT:    vlgvb %r3, %v0, 0
 ; CHECK-NEXT:    risbg %r3, %r3, 48, 176, 15
@@ -122,7 +116,7 @@ define dso_local void @m() local_unnamed_addr #1 {
 ; CHECK-NEXT:    nr %r2, %r0
 ; CHECK-NEXT:    larl %r1, g
 ; CHECK-NEXT:    stc %r2, 0(%r1)
-; CHECK-NEXT:    aghi %r15, 168
+; CHECK-NEXT:    lmg %r13, %r15, 272(%r15)
 ; CHECK-NEXT:    br %r14
 entry:
   %n = alloca i32, align 4

@RKSimon RKSimon closed this Jul 2, 2025
@RKSimon RKSimon deleted the dag-buildvector-freeze-undef branch July 4, 2025 17:17
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